Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a duty cycle correction (DCC) circuit of a semiconductor device.
Double data rate (DDR) technology was developed in order to improve characteristics of a memory system, and in particular a bandwidth of a memory system. A memory system is designed to use rising and falling edges of an internal clock. In this case, a duty cycle of an internal clock is an important factor for maximally securing a timing margin of a high-performance memory system.
When a duty cycle of an internal clock is not accurately maintained at a 50% ratio, an error corresponding to an offset from 50% ratio reduces a timing margin of a high-performance memory system. Therefore, there is a demand for an apparatus which compensates for a distortion of a duty cycle caused by process, voltage, and temperature (PVT) variations. A DCC circuit used in a delay locked loop (DLL) is a circuit which corrects a duty cycle of an internal clock used in a memory system.
FIG. 1 is a block diagram and a timing diagram illustrating the configuration and operation of a DCC circuit of a conventional semiconductor device.
Referring to the block diagram of FIG. 1, the DCC circuit includes a DLL 100 and a phase division unit 120. The DLL 100 compares phases of source clocks CLK and CLKB, which are inputted from the outside, with a phase of a feedback clock FBCLK, which is generated by reflecting/applying an actual delay amount (a replica delay) of a source clock (CLK, CLKB) path in/to a DLL clock DLLCLK. Then, the DLL 100 delays the source clocks CLK and CLKB by a delay time corresponding to a comparison result, and outputs the DLL clock DLLCLK. The phase division unit 120 divides a phase of the DLL clock DLLCLK according to a set division ratio and generates a DLL division clock DIV_DLLCLK.
The timing diagram of FIG. 1 shows that a duty cycle of the DLL clock DLLCLK outputted from the DLL 100 is not maintained at a 50% ratio. That is, the length of a logic high duration of the DLL clock DLLCLK is shorter than the length of a logic low duration of the DLL clock DLLCLK.
If the phase of the DLL clock DLLCLK whose duty cycle is not maintained at the 50% ratio is divided by a half through the phase division unit 120 and then outputted as the DLL division clock DIV_DLLCLK, the duty cycle of the DLL division clock DIV_DLLCLK is accurately maintained at the 50% ratio.
Since the phase division unit 120 makes the duration of one cycle (1 tck) of the DLL clock DLLCLK equal to the duration of a half cycle (½ tck) of the DLL division clock DIV_DLLCLK, the DLL division clock DIV_DLLCLK can always maintain the duty cycle at the 50% ratio even though the logic high duration and the logic low duration, have different lengths in one cycle (1 tck) of the DLL clock DLLCLK.
However, since the DLL division clock DIV_DLLCLK is outputted by dividing the phase of the DLL clock DLLCLK by a half, the DLL division clock DIV_DLLCLK has half the frequency of the DLL clock DLLCLK. When a semiconductor device operates with the DLL division clock DIV_DLLCLK having the lowered frequency, the semiconductor device operates at a low operating speed.
Therefore, in order for the semiconductor device to maintain a desired operating speed by using the clock whose duty cycle is corrected by the above-described conventional method, the semiconductor device is to use the DLL clock outputted from the DLL 100, which has a frequency higher than a frequency of the internal clock according to the operating speed of the semiconductor device.
That is, the above-described DCC method may not be desired for high-speed semiconductor devices which use a relatively high frequency of clock.